1. Field of the Invention
The present invention relates generally to an etching method in semiconductor processing and an etching system for performing the same, and more particularly, to an etching method in semiconductor processing for reducing a pattern loading phenomenon occurring at regions of a semiconductor device during plasma-based dry etching.
2. Description of the Related Art
Recently, the design of devices utilizing semiconductors has progressed rapidly due to the wide spread use of information media such as personal computers, mobile devices, mobile phones, etc. In turn, this rapid progression has demanded semiconductor devices to function at high operating speeds and to have large storage capacities. In order to satisfy such requirements, semiconductor devices with increased integration, reliability, and response time are aggressively being developed. To accomplish a highly integrated device, a reduction of a memory cell size is essential and, accordingly, the reduction of the size and margin of every pattern formed on a substrate of the semiconductor device must also be reduced. However, as a footprint of a semiconductor device decreases, a vertical size of the device, that is, an aspect ratio of elements forming the device, increases in order to maintain performance characteristics, for example, thicker metal interconnections lines to satisfy electrical conductivity requirements.
The technique for forming wiring patterns among various patterns, such as a gate pattern, a bit line, and the like, is regarded as basic for the manufacture of a semiconductor device and is a measure of total processing efficiency. In the current semiconductor device design, the critical dimension (CD) of the patterns of the gate and the bit line is particularly narrow and an aspect ratio of the patterns is especially high. In order to form patterns having a good profile, uniformity of the critical dimension on a whole wafer is necessary and a process change in dry etching according to the pattern density is required to be small.
Generally, a plurality of etching processes are executed using a plasma source in order to form patterns. However, during the execution of the etching, a pattern loading phenomenon occurs, which exhibits different etching rates at different regions due to a difference in pattern densities. That is, the etching at a cell region where the pattern density is high is slow, while an over-etching occurs at a peripheral region where the pattern density is low. This phenomenon becomes more and more severe as the wafer processing progresses. The intensification of the pattern loading phenomenon is caused by by-products generated during implementation of the etching. The by-products generated during the etching of a predetermined material adversely affect a subsequent wafer to be processed.
In particular, when executing a dry etching for forming a gate by means of a dry etching apparatus, such as the DPS Centura system commercially available from Applied Materials of Santa Clara, Calif., which uses a decoupled plasma source in order to form a gate pattern, the etching by-products generated at the cell region where the pattern density is high are not readily removed as the etching proceeds. The by-products affect the etching on the wafer and slow down the etching rate, so that residues remain on the wafer. However, at the peripheral region where the pattern density is low, the removal of the by-products is performed more easily and the generated by-products can be removed in a short time period to provide good etching surroundings, so that the etching is performed to a desired degree. When considering the balance of the etching rates at the two regions of the cell region and the peripheral region, the peripheral region is generally over-etched to attack an underlying layer of a gate oxide layer. This phenomenon will be described in more detail referring to the attached drawings.
FIGS. 1A and 1B are cross-sectional views of a semiconductor device for comparing etching aspects due to pattern loading at various pattern densities. FIG. 1A corresponds to an etching aspect of a gate pattern at a cell region where the pattern density is high, while FIG. 1B corresponds to an etching aspect of a gate pattern at a peripheral region where the pattern density is low.
Referring to FIG. 1A, a gate pattern 14c is formed on a substrate 10 at the cell region by etching polysilicon from the substrate using a photoresist pattern as a mask and by using decoupled plasma. The polysilicon is not completely removed through the etching and a residual polysilicon layer 12 remains on the substrate 10.
Referring to FIG. 1B, a gate pattern 14p is also formed on the substrate 10 at the peripheral region by etching polysilicon using the photoresist pattern as the mask and by using the same decoupled plasma. At the peripheral region, the polysilicon is completely etched and residual polysilicon does not remain, unlike at the cell region. The etching rate at the cell region where the pattern density is high is slowed down gradually when compared with the etching rate at the peripheral region where the pattern density is low during the implementation of the etching for the same time period, leaving residues at the cell region.
If the etching time is controlled to a point when the polysilicon at the cell region is completely removed, an over-etching might be induced at the peripheral region resulting in damage to an underlying layer, that is, a gate oxide layer.
In order to prevent this phenomenon, an EPD (end point detection) system may be used by which an etching end point can be noted by measuring a radiating amount of an inherent wavelength of the material to be etched from the wafer. The determination of the etching time by using the EPD system is accomplished by measuring the lowering of the etching rate at the cell region. Accordingly, the etching time is lengthened gradually according to the progress of the wafer processing. Through the application of this system, the remaining residues at the cell region can be partially prevented. However, since the EPD system utilizes a mean etching time to prevent the phenomenon, it is inevitable that over-etching at the peripheral region where the pattern density is low will occur.
Various other methods have been proposed to improve process characteristics in a plasma chamber.
Korean Laid-Open Patent Publication No. 2001-4243 discloses a cleaning method of a plasma chamber of a semiconductor manufacturing apparatus. This method includes a first step of performing an appropriate process (e.g., an etching process) in a plasma chamber, and a second step of plasma cleaning in order to remove deposited polymer on an inner side wall of the plasma chamber at a bottom bias power of approximately zero or a small value of about 1-800 W, while a running wafer remains in the chamber. According to this method, the cleaning effect onto the inner wall of the chamber is maximized, while an affect onto the wafer by the plasma can be minimized at the same time. In addition, a wet cleaning period of the apparatus can be remarkably increased. This method can be applied to apparatuses other than an etching apparatus, for example, it may be applied to a cleaning of a chamber of a depositing apparatus using plasma.
However, according to this method, the cleaning is executed by setting the bias power to zero or to a small value in order to remove residues after completion of the etching process. Therefore, an etching against even a trace amount of a pattern will generate pattern damage. As a result, this method is applicable to a layer having a pattern of little step after completing the etching process, for example, after completing an etch back process. However, this method is not applicable after completing an etching to form a pattern having a step to some degree.
Korean Laid-Open Patent Publication No. 1999-71110 discloses a method of controlling charged impurities of a plasma etching apparatus for manufacturing a semiconductor device. This method includes the steps of stabilizing a chamber, etching by applying a source power and a bias power to an upper and lower electrode, respectively, forming plasma by providing an inert gas while applying the source power and not applying the bias power and exhausting a cooled gas at the same time, forming plasma by providing an inert gas while not applying the bias power, and transferring a wafer after completion of the etching process.
According to this method, charged particles and falling particles do not adhere onto a surface portion of the wafer after completion of the etching process to improve a yield of the wafer. However, the process is complicated and an undesirable etching might be implemented on the wafer as a side effect as in the above-described method.
Japanese Laid-Open Patent Publication No. Hei 8-111402 discloses a method of dry etching and an apparatus for implementing the method. According to this method, a porous plate having a plurality of minute pores is installed between a plasma generating portion and a sample supporter for supporting a processing body. A bias power is not applied to the sample supporter. Then, ions among the plasma and activated species produced by the plasma are imparted with a drifting direction while passing through the minute pores of the porous plate, to be introduced onto the processing body to accomplish vertical etching.
Although various methods for the plasma dry etching have been proposed as described above, a need exists for an etching method and an etching system for performing the same to reduce the effects of the pattern loading phenomenon caused by the difference of the etching rates between patterns having different pattern densities.